Method of forming silicided gate structure

ABSTRACT

A method of forming a silicided gate on a substrate having active regions is provided. The method comprises forming silicide in the active regions and a portion of the gate, leaving a remaining portion of the gate unsilicided; forming a shielding layer over the active regions and gate after the forming step; forming a coating layer over portions of the shielding layer over the active regions; opening the shielding layer to expose the gate, wherein the coating layer protects the portions of the shielding layer over the active regions during the opening step; depositing a metal layer over the exposed gate; and annealing to cause the metal to react with the gate to silicidize at least a part of the remaining portion of the gate.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. patent application Ser. No.10/846,278, filed May 13, 2004, entitled “Method of Forming SilicidedGate Structure”, now U.S. Pat. No. ______, the entirety of which ishereby incorporated by reference herein.

FIELD OF THE INVENTION

The present invention relates to semiconductor fabrication and moreparticularly to methods of forming field effect transistors havingsilicided regions.

BACKGROUND OF THE INVENTION

The principle way of reducing contact resistance between polysilicongates and source/drain regions and interconnect lines is by forming ametal silicide atop the source/drain regions and the gate electrodesprior to application of the conductive film for formation of the variousconductive interconnect lines. Presently, the most common metal silicidematerials are CoSi₂ and TiSi₂, typically formed by the so calledsalicide (self-aligned silicide) process. In the salicide process, athin layer of a metal, such as titanium, is blanket deposited over thesemiconductor substrate, specifically over exposed source/drain and gateelectrode regions. The wafer is then subjected to one or more annealingsteps, for example at a temperature of 800° C. or higher for titanium.This annealing process causes the metal to selectively react with theexposed silicon of the source/drain regions and the gate electrodes,thereby forming a metal silicide (e.g., TiSi₂). The process is referredto as the self-aligned silicide process because the silicide layer isformed only where the metal material directly contacts the siliconsource/drain regions and the polycrystalline silicon (polysilicon) gateelectrode. Following the formation of the silicide layer, the unreactedmetal is removed and an interconnect process is performed to provideconductive paths, such as by forming via holes through a depositedinterlayer dielectric and filling the via holes with a conductivematerial, e.g., tungsten.

The thickness of the silicide layer is an important parameter because athin silicide layer is more resistive than a thicker silicide layer ofthe same material. Therefore, a thicker silicide layer increasessemiconductor speed. The formation of a thick silicide layer, however,may cause a high junction leakage current in the active regions and lowreliability, particularly when forming ultra-shallow junctions. Theformation of a thick silicide layer consumes silicon from the underlyingsemiconductor substrate such that the thick silicide layer approachesand even shorts the ultra-shallow junction, thereby generating a highjunction leakage current.

It is desirable to also lower the resistance of the gate electrode toincrease the speed of the device. The greater the amount of siliconconverted into silicide in the gate electrode, the lower the resistancewill be in the gate electrode. Silicided gate electrodes also eliminateproblems associated with boron penetration from the polysilicon gateelectrode into the gate oxide of PMOS devices and avoid deviceperformance degradation due to the depletion effect. Formation ofsilicide in the gate electrode simultaneously with the source/drainregions leads to the risk of spiking in the source/drain regions if thecomplete silicidation of the gate electrode is attempted. Theconventional salicide process, therefore, suffers from a very narrowprocess window due to the strong likelihood that exposure of the metaland silicon to rapid thermal annealing conditions sufficient tocompletely silicidize a gate electrode will also cause the silicide inthe source/drain region to spike and reach the bottom of the junction,undesirably causing leakage.

Various methods have been suggested for forming fully silicided gateelectrodes. U.S. Pat. No. 6,562,718 to Xiang et al. describes a methodof forming a fully silicided gate electrode. Xiang et al. proposesimultaneously forming a silicide region in the source/drain regions andpartially within the gate electrode. A silicon oxide shielding layer isthen deposited over the substrate and opened by chemical mechanicalpolishing (CMP) to expose the gate electrode, leaving the source/drainregions covered by the remaining portion of the shielding layer.Silicidation of the gate electrode is then completed. The Xiang et al.process suffers from several problems. The CMP step adds significantprocess costs to the fabrication method. Further, the CMP step adverselyeffects process control. Specifically, the CMP step is not highlyselective between the oxide shielding layer and the polysilicon gate.Therefore, the height of the polysilicon gate cannot be controlledeffectively using the process of Xiang et al. There remains a need for amethod of forming fully silicided gate electrodes that affords greaterprocess control.

SUMMARY OF THE INVENTION

A method of forming a silicided gate on a substrate having activeregions is provided. The method comprises forming silicide in the activeregions and a portion of the gate, leaving a remaining portion of thegate unsilicided; forming a shielding layer over the active regions andgate after the forming step; forming a coating layer over portions ofthe shielding layer over the active regions; opening the shielding layerto expose the gate, wherein the coating layer protects the portions ofthe shielding layer over the active regions during the opening step;depositing a metal layer over the exposed gate; and annealing to causethe metal to react with the gate to silicidize at least a part of theremaining portion of the gate.

The above and other features of the present invention will be betterunderstood from the following detailed description of the preferredembodiments of the invention that is provided in connection with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings illustrate preferred embodiments of theinvention, as well as other information pertinent to the disclosure, inwhich:

FIGS. 1-11 schematically illustrate sequential phases of forming a fullysilicided gate in accordance with an embodiment of the presentinvention.

DETAILED DESCRIPTION

The method steps described below do not form a complete process flow formanufacturing integrated circuits. The present embodiments can bepracticed in conjunction with integrated circuit fabrication techniquescurrently used or known in the art or later developed, and only so muchof the commonly practiced process steps are included as are necessaryfor an understanding of the described embodiments. The figures representcross-section portions of a semiconductor chip or a substrate duringfabrication and are not drawn to scale, but instead are drawn toillustrate the features of the described embodiments.

Sequential steps of an exemplary embodiment of a method of formingsilicide regions in a semiconductor substrate, specifically a fullysilicided gate, are described below with respect to the schematicillustrations of FIGS. 1-11. Similar reference numerals denote similarfeatures. Referring first to FIG. 1, a conventional transistor structureis provided comprising a substrate 10 doped with either an N-typeimpurity or P-type impurity and source/drain regions 11 comprisingshallow extension regions 11A and heavily doped regions 11B doped witheither a P-type impurity or an N-type impurity. In an exemplaryembodiment, the substrate comprises crystalline silicon, e.g.,monocrystalline silicon. The substrate 10 can be, for example,silicon-germanium substrate, III-V compound substrate, silicon oninsulator (SOI) substrate or other substrate. As is common, thesource/drain regions 11 have a conductivity opposite to that of thesubstrate. The source/drain regions 11 are formed by forming gateelectrode 13 on the substrate 10 with gate dielectric layer 12, e.g., agate oxide such as silicon dioxide, therebetween. Using the gateelectrode 13 as a mask, shallow extension regions 11A are formed.Dielectric sidewall spacers 14 are then formed on the side surfaces ofthe gate electrode 13. Dielectric sidewall spacers may comprise anysuitable dielectric material, such as silicon dioxide, silicon nitride,or a composite of silicon dioxide and silicon nitride. Ion implantationis then conducted, using the gate electrode 13 and sidewall spacers 14as a mask to form heavily doped regions 11B.

Referring to FIG. 2, metal layer 20, such as nickel, is blanketdeposited over at least the exposed portions of the active source/drainregions 11, i.e., on the heavily doped regions 11B, and, in oneembodiment, on the upper surface of the gate electrode 13, which maycomprise polycrystalline silicon or amorphous silicon. In oneembodiment, the gate electrode has a height between about 500-2800 Å,more preferably 1000-2000 Å. The metal layer 20 can be deposited in anymanner, such as by chemical vapor deposition (CVD) or sputtering. Anexemplary thickness of metal layer 20 is between about 80-200 Å, whichwill produce silicide in the substrate 10 to a depth of about 150-400 Åafter annealing.

Referring to FIG. 3, an annealing step is performed, typically a rapidthermal annealing (RTA) step. The annealing step may take place at atemperature of about 350° C. to about 700° C. for about 10 to about 90seconds when nickel is employed as the metal. Other rapid thermal annealparameters may be used depending on the selected metal and the silicidequantities desired. Upon annealing, metal silicide layers 30, 31, e.g.,nickel silicide, form in the source/drain regions 11 and the gateelectrode 13, respectively. Preferably, the thickness of the silicidelayers 30, 31 in the source/drain regions can be tailored or optimizedby controlling the thickness of the deposited nickel layer 20 and theRTA parameters (e.g., temperature and time).

Referring to FIG. 4, any unreacted metal 32 (FIG. 3) is removed from thesubstrate 10, leaving a clean upper surface 60 on the gate. In oneembodiment, the unreacted metal is removed by a wet chemical etch, suchas with a sulfuric peroxide mixture H₂SO₄:H₂O (3:1) with deionized H₂Oat a temperature of 100° C. The removal rate of nickel at the 3:1 ratiois about 10,000 Å/minute. This exemplary wet chemical etch exhibits highselectivity for the unreacted nickel 32 relative to the nickel silicidelayers 30, 31.

Referring to FIG. 5, a shielding layer 50 is deposited over thesemiconductor device. In one embodiment, shielding layer 50 comprisessilicon oxide or other material that will not react with thesubsequently deposited metal, thereby protecting the silicidizedsource/drain regions 30 from further silicidation during subsequentcompletion of the silicidation of the gate. Shielding layer 50 may beformed by chemical vapor deposition, for example. In one embodiment, thelayer 50 is formed to a thickness between about 50-500 Å.

Referring to FIG. 6, a coating layer 100 is formed over the substrate 10shown. In an exemplary embodiment, the coating layer 100 comprises apolymer, preferably an organic polymer such as a 193 nm or 248 nmphotoresist. The coating layer is preferably formed to a thickness so asto not cover the shielding layer 50 in a region over the gate but to besufficiently thick so as to substantially protect (i.e., prevent etchthrough) of the shielding layer 50 over silicided regions 30 duringopening of the shielding layer 50 over the gate electrode (as describedbelow). In one embodiment, for a gate electrode (i.e., polysiliconregions 13 and silicide regions 31 in FIG. 6) having a thickness betweenabout 300-1500 Å, the coating layer 100 has a thickness between about300-1500 Å.

Referring to FIG. 7, an opening in the shielding layer 50 is formed,thereby exposing the top surface 60 of the gate electrode. In oneembodiment, the opening is formed through the shielding layer 50 usingan etch back process, such as: pressure: 4-500 mTorr; power: 20-1000 W;chemistry: CF based (e.g., CF₄ or CHF₃ or CH₂F₂ or CH₃F) at 10-200 sccm,Argon at 10-500 sccm, and O₂ at 1-50 sccm. Using an etch processeliminates the need for a chemical mechanical polishing step to exposethe gate electrode for further silicidation as well as the cleaningsteps that typically follow the CMP process. Excellent alignment canalso be achieved using the masks utilized in formation of the gate

Referring to FIG. 8, the photoresist layer 100 is then removed to leavethe remainder of shielding layer 50, which includes an opening thatexposes the top surface 60 of the gate electrode. In one embodiment, thephotoresist layer 100 is removed using an oxygen (O₂) ashing process. Inone embodiment, the flow parameters are as follows: N₂ or N₂H₂ or H₂ at30-500 sccm and O₂ at 100-500 sccm.

Referring to FIG. 9, a metal layer 70, such as nickel, is then blanketdeposited over the semiconductor device including the exposed surface 60of the gate electrode 13 and the remaining portions of shielding layer50. The deposited metal layer 70 is deposited to a thickness to, onceannealed, silicidize at least a part of the remaining portion of thegate electrode. In a preferred embodiment, the deposited metal layer 70is at least of sufficient thickness that, once annealed, the layer 70reacts with the gate electrode to silicidize the remaining portions ofthe gate electrode, thereby forming a fully silicidized gate. As theratio of nickel to silicide is about 1:3 or 1:4, for a 1000 Å gate,about 250-400 Å layer of nickel is sufficient to fully silicidize thegate electrode 13 in this embodiment. This thickness may be reducedsomewhat, depending on the depth of the initial silicidation 31 in thegate electrode 13 prior to this second silicidation step. Forming themetal layer to a greater thickness, however, ensures a sufficient sourceof metal for silicidizing the gate electrode 13. Because the gateelectrode height can be more easily controlled, compared with exposingthe gate electrode by chemical mechanical polishing, the silicidation ofthe remaining portions of the gate electrode may also be more easilycontrolled.

Referring to FIG. 10, a rapid thermal anneal process is again applied tothe substrate causing the metal 70 to react with the gate electrode 13.The metal 70 diffuses into the gate electrode 13 to silicidize theremaining portion of the gate, thereby fully silicidizing the gateelectrode 13. By “fully silicidize” or “fully silicided” it is meantthat the gate electrode is substantially silicided, meaning, in oneembodiment, silicide forms in at least 90-100 percentage of the heightgate, and more preferably at least 95-100 percentage of the height ofthe gate. Although nickel has been described as a preferred metal forthe embodiments described herein, other metals or alloys that formsilicides and are predominant diffusion species may be used, such asPalladium (Pd), Chromium (Cr), Cobalt (Co), Titanium (Ti), etc.Annealing process parameters and metal thickness may change independence on the metal 70 selected.

Referring to FIG. 11, the unreacted metal layer 81 and the shieldinglayer 50 are removed, thereby providing a fully silicidized gateelectrode 80 and silicided source/drain regions 30. Etching may beperformed, for example, in a two-step etching process. A wet chemicaletch that is highly selective for unreacted metal relative to thesilicide, such as previously described for nickel, is employed to removethe unreacted metal 81. The shield layer 50 may then be removed usingconventional etching techniques suitable for removing that materialrelative to the spacers 14 and silicide regions, for example, phosphoricacid etching may be employed. Alternatively, a single etch that etchesboth the unreacted metal 81 and the shield layer 50 selectively relativeto the silicide regions 80, 30 may be employed.

Referring again to FIG. 6, polymer layer 100 can be formed in severalways. In a first embodiment, a low viscosity polymer, such as an organicpolymer comprising a 193 nm or 248 nm photoresist, is flowed over thesubstrate in a volume sufficient to form a layer 100 that cover thesource/drain regions but not the top surface of the gate electrode. Inone embodiment, the polymer is applied by spin coating and the thicknesscan be controlled by volume and spin speed. In a second embodiment, apolymer layer is deposited over the substrate in a thickness sufficientto cover both source/drain regions and the gate electrode. The polymerlayer is then etched back to the desired thickness, exposing theshielding layer 50 over the gate electrode top surface. In oneembodiment, the polymer layer comprises a 193 nm or 248 nm photoresistor other organic polymer that can be removed by a wet or dry sappingprocess, preferably an oxygen plasma etching. The layer is then etchedback at a pressure between about 5-100 mTorr, power between about50-1000 Watts, using a O₂ base with an additional etchant gas, such asHBr, Cl₂, He, or Argon at a temperature between about 20-100° C. In athird embodiment, layer 100 may be formed to the desired thicknessthrough a baking and developing process. Generally, the organic polymerwill react with the development solution at a high temperature,providing at least two parameters that can be used to control thepolymer thickness—the amount of development solution and temperature.

In a possible alternative embodiment, only the silicide regions 30 areinitially formed as shown in FIG. 3, leaving gate 30 initiallyunsilicided. This may be accomplished by selectively depositing metallayer 20 or using a shielding layer over gate 13 that is etched toexpose the active regions, or, in one embodiment, using a removable“dummy” gate electrode during silicidation of the active regions.Subsequently, the process steps described above in connection with FIGS.5-11 are employed, only metal layer 70 is deposited to a thicknesssufficient to fully silicidize gate 13 upon annealing. This embodimentallows for the use of different metals in forming silicide regions 30and 80 if desired.

The manufacturing process described herein is adaptable to manufacturingany of the various types of semiconductor devices, particularly advanceddeep-submicron CMOS devices, such as 0.1 microns with ultra-shallowjunctions, e.g., above 500 Å to about 2000 Å in depth, whilesignificantly improving the reliability of ultra-shallow junctions.Parasitic, sheet and contact resistance between the active regions andthe gate electrode and interconnects is achieved without increasingjunction leakage current.

The method described herein also provides for excellent control of thegate electrode height during the silicidation process. The process hasan improved process window for exposing the top surface of the gateelectrode in a two-step silicidation formation process, therebyfacilitating improved control of the silicidation process, whichprovides improved fully silicided gates, and consequent benefitsthereof, such as lower gate electrode resistance, improved device speed,prevention or reduction of boron migration into the gate electrode andreduction or elimination of the depletion effect, without high junctionleakage current or spiking.

As noted, the method provides for excellent control of the gateelectrode height in forming increased silicidation in gate electrodes,particularly when compared to a process using a chemical mechanicalpolish as described above in the Background of the Invention section.Substantially uniform gate electrode heights can be achieved acrossregions in an integrated circuit. In a typical integrated circuit, thereare both areas of dense lines and isolated lines (iso lines) within bothactive (OD) and shallow trench isolation (STI) regions. In oneembodiment, the present method described above utilizes an etch processin exposing gates for silicidation. The etch process provides asubstantially uniform etch rate with respect to both areas of dense andnon-dense (e.g., isolated) patterns with these regions. Conversely, CMPpolishing rates tend to depend on pattern density, thereby providingdifferent polishing rates for areas of dense and less dense patterningwithin both OD and STI regions. In one embodiment, the gate heightdifference between gates in dense and less dense or non-dense areas inthe OD and/or STI regions is less than 10%. In this embodiment, at leastsome, if not all, of the gates in these regions are fully silicided.

Although the invention has been described in terms of exemplaryembodiments, it is not limited thereto. Rather, the appended claimsshould be construed broadly to include other variants and embodiments ofthe invention that may be made by those skilled in the art withoutdeparting from the scope and range of equivalents of the invention

1. An integrated circuit comprising a substrate having a plurality ofgates formed thereon in a patterned region, at least some of said gatesformed in an area of relative dense patterning in said patterned regionand at least some of said gates formed in an area of relative non-densepatterning in said patterned region, and associated active regionsformed therein, said active regions having a silicide formed therein andsaid gates having a silicide formed therein, wherein said gate silicideis thicker than said silicide formed in said active regions, wherein agate height difference between said gates in said patterned region isless than 10%.
 2. The integrated circuit of claim 1, wherein at leastsome of said gates are fully silicided.